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functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit 10 msps monolithic a/d converter ad872a features monolithic 12-bit 10 msps a/d converter low noise: 0.26 lsb rms referred-to-input no missing codes guaranteed differential nonlinearity error: 0.5 lsb signal-to-noise and distortion ratio: 68 db spurious-free dynamic range: 75 db power dissipation: 1.03 w complete: on-chip track-and-hold amplifier and voltage reference twos complement binary output data out-of-range indicator 28-lead ceramic dip or 44-terminal leadless chip carrier package product description the ad872a is a monolithic 12-bit, 10 msps analog-to-digital converter with an on-chip, high performance track-and-hold amplifier and voltage reference. the ad872a uses a multistage differential pipelined architecture with error correction logic to provide 12-bit accuracy at 10 msps data rates and guarantees no missing codes over the full operating temperature range. the ad872a is a redesigned version of the ad872 which has been optimized for lower noise. the ad872a is pin compatible with the ad872, allowing the parts to be used interchangeably as sys- tem requirements change. the low noise input track-and-hold (t/h) of the ad872a is ideally suited for high-end imaging applications. in addition, the t/hs high input impedance and fast settling characteristics al- low the ad872a to easily interface with multiplexed systems that switch multiple signals through a single a/d converter. the dynamic performance of the t/h also renders the ad872a suit- able for sampling single channel inputs at frequencies up to and beyond the nyquist rate. the ad872a provides both reference output and reference input pins, allowing the onboard reference to serve as a system reference. an external reference can also be chosen to suit the dc accuracy and temperature drift require- ments of the application. a single clock input is used to control all internal conversion cycles. the digital output data is pre- sented in twos complement binary output format. an out-of- range signal indicates an overflow condition, and can be used with the most significant bit to determine low or high overflow. the ad872a is fabricated on analog devices abcmos-l process that utilizes high speed bipolar and cmos transistors on a single chip. the ad872a is packaged in a 28-lead ceramic dip and a 44- terminal leadless ceramic surface mount package (lcc). opera- tion is specified from 0 c to +70 c and C55 c to +125 c. product highlights the ad872a offers a complete single-chip sampling, 12-bit 10 msps analog-to-digital conversion function in a 28-lead dip or 44-terminal lcc. low noise the ad872a features 0.26 lsb rms referred to- input noise. low power the ad872a at 1.03 w consumes a fraction of the power of presently available hybrids. on-chip track-and-hold (t/h) the low noise, high imped- ance t/h input eliminates the need for external buffers and can be configured for single-ended or differential inputs. ease of use the ad872a is complete with t/h and voltage reference and is pin-compatible with the ad872. out of range (otr) the otr output bit indicates when the input signal is beyond the ad872as input range. 4 4 3 4 correction logic +2.5v reference output buffers * oen otr * msb bit2?it12 ref gnd msb av dd agnd dgnd av ss dv dd v ina v inb clock ref in * only available on 44-terminal surface mount package ad872a t/h dac a/d a/d t/h dac a/d t/h a/d dac * drv dd * drgnd ref out + + + one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997
ad872aCspecifications rev. a C2C dc specifications (t min to t max , av dd = + 5 v, dv dd = +5 v, av ss = C5 v, f sample = 10 mhz unless otherwise noted) parameter j grade 1 s grade 1 units resolution 12 12 bits min max conversion rate 10 10 mhz min input referred noise 0.26 0.26 lsb rms typ accuracy integral nonlinearity (inl) 1.75 1.75 lsb typ differential nonlinearity (dnl) 0.5 0.5 lsb typ no missing codes 12 12 bits guaranteed zero error (@ +25 c) 2 0.75 0.75 % fsr max gain error (@ +25 c) 2 1.25 1.25 % fsr max temperature drift zero error 0.15 0.3 % fsr max gain error 3, 4 0.80 1.75 % fsr max gain error 3, 5 0.25 0.50 % fsr max power supply rejection 6 av dd , dv dd (+5 v 0.25 v) 0.125 0.125 % fsr max av ss (C5 v 0.25 v) 0.125 0.125 % fsr max analog input input range 1.0 1.0 v max input resistance 50 50 k w typ input capacitance 10 10 pf typ internal voltage reference output voltage 2.5 2.5 v typ output voltage tolerance 20 40 mv max output current (available for external loads) 2.0 2.0 ma typ (external load should not change during conversion) reference input resistance 5 5 k w power supplies supply voltages av dd +5 +5 v ( 5% av dd operating) av ss C5 C5 v ( 5% av ss operating) dv dd +5 +5 v ( 5% dv dd operating) drv dd 7 +5 +5 v ( 5% drv dd operating) supply current iav dd 91 92 ma max (85 ma typ) iav ss 147 150 ma max (115 ma typ) idv dd 20 21 ma max (7 ma typ) idrv dd 7 22ma power consumption 1.03 1.03 w typ 1.25 1.3 w max notes 1 temperature ranges are as follows: j grade: 0 c to +70 c, s grade: C55 c to +125 c. 2 adjustable to zero with external potentiometers (see zero and gain error calibration section). 3 +25 c to t min and +25 c to t max . 4 includes internal voltage reference drift. 5 excludes internal voltage reference drift. 6 change in gain error as a function of the dc supply voltage (v nominal to v min , v nominal to v max ). 7 lcc package only. specifications subject to change without notice.
ac specifications (t min to t max , av dd = + 5 v, dv dd = +5 v, av ss = C5 v, f sample = 10 mhz unless otherwise noted) 1 rev. a C3C ad872a parameter j grade s grade units signal-to-noise & distortion ratio (s/n+d) f input = l mhz 68 68 db typ 61 61 db min f input = 4.99 mhz 66 66 db typ signal-to-noise ratio (snr) f input = 1 mhz 69 69 db typ f input = 4.99 mhz 67 67 db typ total harmonic distortion (thd) f input = 1 mhz C74 C74 db typ C63 C62 db max f input = 4.99 mhz C72 C72 db typ spurious-free dynamic range (sfdr) f input = l mhz 75 75 db typ f input = 4.99 mhz 74 74 db typ intermodulation distortion (imd) 2 second order products C80 C80 db typ third order products C73 C73 db typ full power bandwidth 35 35 mhz typ small signal bandwidth 35 35 mhz typ aperture delay 6 6 ns typ aperture jitter 16 16 ps rms typ acquisition to full-scale step 40 40 ns typ overvoltage recovery time 40 40 ns typ notes 1 f input amplitude = C0.5 db full scale unless otherwise indicated. all measurements referred to a 0 db (1.0 v pk) input signal unless otherwise indicated. 2 fa = 1.0 mhz, fb = 0.95 mhz with t sample = 10 mhz. specifications subject to change without notice. digital specifications parameter symbol j, s grades units logic inputs high level input voltage v ih +2.0 v min low level input voltage v il +0.8 v max high level input current (v in = dv dd )i ih 115 m a max low level input current (v in = 0 v) i il 115 m a max input capacitance c in 5 pf typ logic output high level output voltage (i oh = 0.5 ma) v oh +2.4 v min low level output voltage (i ol = 1.6 ma) v ol +0.4 v max output capacitance c out 5 pf typ leakage (three state, lcc only) iz 10 m a max specifications subject to change without notice. (t min to t max , av dd = + 5 v, dv dd = +5 v, av ss = C5 v, f sample = 10 mhz unless otherwise noted)
rev. a C4C ad872a switching specifications parameter symbol j, s grades units clock period 1 t c 100 ns min clock pulsewidth high t ch 45 ns min clock pulsewidth low t cl 45 ns min clock duty cycle 2 40 % min (50% typ) 60 % max output delay t od 10 ns min (20 ns typ) pipeline delay (latency) 3 clock cycles data access time (lcc package only) 2 t dd 50 ns typ (100 pf load) output float delay (lcc package only) 2 t hl 50 ns typ (10 pf load) notes 1 conversion rate is operational down to 10 khz without degradation in specified performance. 2 see section on three-state outputs for timing diagrams and applications information. specifications subject to change without notice. clock n+1 data n data n+1 vin n n n+1 t od t c bit 2?2 msb, otr t ch t cl figure 1. timing diagram absolute maximum ratings 1 parameter with respect to min max units av dd agnd C0.5 +6.5 volts av ss agnd C6.5 +0.5 volts dv dd , drv dd 2 dgnd, drgnd 2 C0.5 +6.5 volts drv dd 2 dv dd C6.5 +6.5 volts drgnd dgnd C0.3 +0.3 volts agnd dgnd C1.0 +1.0 volts av dd dv dd C6.5 +6.5 volts clock input, oen 2 dgnd C0.5 dv dd + 0.5 volts digital outputs dgnd C0.5 dv dd + 0.3 volts v ina , v inb , ref in agnd C6.5 +6.5 volts ref in agnd av ss av dd volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposu re to absolute maximum ratings for extended periods may affect device reliability. 2 lcc package only. (t min to t max with av dd = +5 v, dv dd = +5 v, drv dd = +5 v, av ss = C5 v; v il = 0.8 v, v in = 2.0 v, v ol = 0.4 v and v oh = 2.4 v)
rev. a C5C ad872a 7 17 8 9 10 11 12 13 14 15 16 1 640 44 41 42 43 2 3 4 5 29 39 30 31 32 33 34 35 36 37 38 18 28 19 20 21 22 23 24 25 26 27 ad872a top view (not to scale) otr ref gnd msb av dd agnd dgnd av ss av dd v ina v inb clk ref in ref out bit 12 (lsb) av ss agnd drgnd dv dd bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 drv dd drv dd drgnd oen bit 1 (msb) nc nc nc nc nc nc nc nc nc nc nc nc = no connect pin description dip lcc symbol pin no. pin no. type name and function v ina 1 1 ai (+) analog input signal on the differential input amplifier. v inb 2 2 ai (C) analog input signal on the differential input amplifier. av ss 3, 25 5, 40 p C5 v analog supply. av dd 4 6, 38 p +5 v analog supply. agnd 5, 24 9, 36 p analog ground. dgnd 6, 23 10 p digital ground. dv dd 7, 22 33 p +5 v digital supply. bit 12 (lsb) 8 16 do least significant bit. bit 2Cbit 11 18C9 26C17 do data bits 2 through 11. msb 19 29 do inverted most significant bit. provides twos complement output data format. otr 20 30 do out of range is active high on the leading edge of code 0 or the trailing edge of code 4096. see output data format table iii. clk 21 31 di clock input. the ad872a will initiate a conversion on the rising edge of the clock input. see the timing diagram for details. ref out 26 41 ao +2.5 v reference output. tie to ref in for normal operation. ref gnd 27 42 ai reference ground. ref in 28 43 ai reference input. +2.5 v input gives 1 v full-scale range. drv dd n/a 12, 32 p +5 v digital supply for the output drivers. nc n/a 3, 4, 7, 8, 14, 15, no connect. 28, 35, 37, 39, 44 drgnd n/a 11, 34 p digital ground for the output drivers. (see section on power supply decoupling for details on drv dd and drgnd.) oen n/a 13 di output enable. see the three state output timing diagram for details. bit 1 n/a 27 do most significant bit. type: ai = analog input; ao = analog output; di = digital input; do = digital output; p = power; n/a = not available on 28-lead dip. only available on 44-terminal surface mount package. pin configurations 28-lead ceramic dip 44-terminal lcc 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad872a v ina av ss ref out ref gnd ref in v inb av ss av dd dv dd dgnd agnd agnd dgnd dv dd bit 12 (lsb) bit 11 bit 10 msb otr clk bit 9 bit 8 bit 7 bit 6 bit 2 bit 5 bit 4 bit 3
rev. a C6C ad872a definitions of specifications linearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential linearity error (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. zero error the major carry transition should occur for an analog value 1/2 lsb below analog common. zero error is defined as the deviation of the actual transition from that point. the zero error and temperature drift specify the initial deviation and maximum change in the zero error over temperature. gain error the first code transition should occur for an analog value 1/2 lsb above nominal negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal positive full scale. gain error is the deviation of the actual differ- ence between first and last code transitions and the ideal differ- ence between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (+25 c) value to the value at t min or t max . power supply rejection the specifications show the maximum change in the converters full scale as the supplies are varied from nominal to min/max values. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. aperture delay aperture delay is a measure of the track-and-hold amplifier (tha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. overvoltage recovery time overvoltage recovery time is defined as that amount of time re- quired for the adc to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converters range. dynamic specifications signal-to-noise and distortion (s/n+d) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is ex- pressed as a percentage or in decibels. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 . . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa C fb), and the third or- der terms are (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (2 fb C fa). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. the two signals are of equal amplitude and the peak value of their sums is C0.5 db from full scale. the imd prod- ucts are normalized to a 0 db input signal. full-power bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 db for a full-scale input. spurious free dynamic range the difference, in db, between the rms amplitude of the input signal and the peak spurious signal. ordering guide model temperature range package option 1 ad872ajd 0 c to +70 c d-28 ad872aje 0 c to +70 c e-44a ad872asd 2 C55 c to +125 c d-28 ad872ase 2 C55 c to +125 c e-44a notes 1 d = ceramic dip, e = leadless ceramic chip carrier. 2 mil-std-883 version will be available; contact factory.
rev. a C7C figure 4. ad872a typical fft, f in = 1 mhz, f in amplitude = C0.5 db figure 5. ad872a typical fft, f in = 1 mhz, f in amplitude = C6 db dynamic characteristicsCsample rate: 10 mspsCad872a ?0 ?5 ?0 ?5 ?0 ?5 2nd harmonic thd 3rd harmonic amplitude ?db 10 5 10 6 10 7 input frequency ?hz figure 3. ad872a distortion vs. input frequency, full-scale input 10 5 10 6 10 7 s/(n+d) db input frequency ?hz 70 68 66 64 62 60 58 56 54 52 50 ?.0 db ?.5 db figure 2. ad872a s/(n+d) input frequency 15db/ div 1 9 2 8 3 4 6 5 7 f in = 1mhz f in amplitude = ?.5db thd = 73db s/(n+d) = 68db snr = 70db sfdr = 73db 2nd ?3 3rd ?2 4th ?7 5th ?0 6th ?2 7th ?5 8th ?5 9th ?3 harmonics ?db 15db/ div 1 9 2 8 3 7 4 6 5 f in = 1mhz f in amplitude = ?.0db thd = ?7db s/(n+d) = 65db snr = 65db sfdr = 81db 2nd ?1 3rd ?7 4th ?1 5th ?4 6th ?8 7th ?0 8th ?0 9th ?4 harmonics ?db
rev. a C8C ad872aCdynamic characteristicsCsample rate: 10 msps figure 6. ad872a typical fft, f in = 750 khz figure 7. ad872a typical fft, f in = 5 mhz figure 8. ad872a output code histogram for dc input figure 9. ad872a code probability at a transition 15db/ div f in = 750khz f in amplitude = ?.5db thd = ?4db s/(n+d) = 69db snr = 71db sfdr = 75db 9 2 8 3 7 4 6 5 1 2nd ?5 3rd ?8 4th ?3 5th ?7 6th ?6 7th ?0 8th ?1 9th ?4 harmonics ?db 15db/ div f in = 5mhz f in amplitude = ?.5db thd = ?4db s/(n+d) = 65db snr = 65db sfdr = 69db 9 4 5 2 1 2nd ?5 3rd ?3 4th ?5 5th ?5 6th ?9 7th ?7 8th ?0 9th ?2 harmonics ?db ? 0 +1 deviation from correct code ?lsb 700000 600000 500000 400000 300000 200000 100000 0 number of code hits 618061 15170 19559 100 90 80 70 60 50 40 30 20 10 0 code x code x + 1 0.26 lsb rms 100 x p( 3 code x + 1)
rev. a C9C ad872a theory of operation the ad872a is implemented using a 4-stage pipelined multiple flash architecture. a differential input track-and-hold amplifier (tha) acquires the input and converts the input voltage into a differential current. a 4-bit approximation of the input is made by the first flash converter, and an accurate analog representa- tion of this 4-bit guess is generated by a digital-to-analog con- verter. this approximation is subtracted from the tha output to produce a remainder, or residue. this residue is then sam- pled and held by the second tha, and a 4-bit approximation is generated and subtracted by the second stage. once the second tha goes into hold, the first stage goes back into track to acquire a new input signal. the third stage provides a 3-bit ap- proximation/subtraction operation, and produces the final resi- due, which is passed to a final 4-bit flash converter. the 15 output bits from the 4 flash converters are accumulated in the correction logic block, which adds the bits together using the appropriate correction algorithm, to produce the 12-bit output word. the digital output, together with overrange indicator, is latched into an output buffer to drive the output pins. the additional tha inserted in each stage of the ad872a architecture allows pipelining of the conversion. in essence, the converter is converting multiple inputs simultaneously, process- ing them through the converter chain serially. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the con- version to be fully processed and appear at the output. this pipeline delay is often referred to as latency, and is not a con- cern in most applications, however there are some cases where it may be a consideration. for example, some applications call for the a/d converter to be placed in a high speed feedback loop, where its input is servoed to provide a desired result at the digi- tal output (e.g., offset calibration or zero restoration in video applications). in these cases the three clock cycle delay through the pipeline must be accounted for in the loop stability calcula- tions. also, because the converter is working on three conver- sions simultaneously, major disruptions to the part (such as a large glitch on the supplies or reference) may corrupt three data samples. finally, there will be a minimum clock rate below which the tha droop corrupts the signal in the pipeline. in the case of the ad872a, this minimum clock rate is 10 khz. the high impedance differential inputs of the ad872a allow a variety of input configurations (see applying the ad872a), the ad872a converts the voltage difference between the v ina and v inb pins. for single-ended applications, one input pin (v ina or v inb ) may be grounded, but even in this case the differ- ential input can provide a performance boost: for example, for an input coming from a coaxial cable, v inb can be tied to the shield ground, allowing the ad872a to reject shield noise as common mode. the high input impedance of the device mini- mizes external driving requirements and allows the user to exter- nally select the appropriate termination impedance for the application. the ad872a clock circuitry uses both edges of the clock in its internal timing circuitry (see spec page for exact timing require- ments). the ad872a samples the analog input on the rising edge of the clock input. during the clock low time (between the falling edge and rising edge of the clock) the input tha is in track mode; during the clock high time it is in hold. system dis- turbances just prior to the rising edge of the clock may cause the part to acquire the wrong value, and should be minimized. while the part uses both clock edges for its timing, jitter is only a significant issue for the rising edge of the clock (see clock input section). applying the ad872a analog inputs the ad872a features a high impedance differential input that can readily operate on either single-ended or differential input signals. table i summarizes the nominal input voltage span for both single-ended and differential modes, assuming a 2.5 v reference input. table i. input voltage span v ina v inb v ina Cv inb single-ended +1 v gnd +1 v (positive full scale) C1 v gnd C1 v (negative full scale) differential +0.5 v C0.5 v +1 v (positive full scale) C0.5 v +0.5 v C1 v (negative full scale) figure 10 shows an approximate model for the analog input cir- cuit. as this model indicates, when the input exceeds 1.6 v (with respect to agnd), the input device may saturate, causing the input impedance to drop substantially and significantly re- ducing the performance of the part. input compliance in the negative direction is somewhat larger, showing virtually no deg- radation in performance for inputs as low as C1.9 v. +5v 1.75ma +1.6v 5pf C1.9v C5v 1.75ma v ina or v inb 6 1v ad872a figure 10. ad872a equivalent analog input circuit figure 11 illustrates the effect of varying the common-mode voltage of a C0.5 db input signal on total harmonic distortion. ? ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 1.0 cm input voltage ?v 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 thd db figure 11. ad872a total harmonic distortion vs. cm input voltage, f in = 1 mhz, fs = 10 msps
rev. a C10C ad872a figure 12 shows the common-mode rejection performance vs. frequency for a 1 v p-p common-mode input. this excellent common-mode rejection over a wide bandwidth affords the user the opportunity to eliminate many potential sources of input noise as common mode by using the differential input structure of the ad872a. input frequency C hz C20 C30 C40 C50 C60 C70 C80 C90 C100 cmr C db 10 5 10 6 10 7 10 8 figure 12. common-mode rejection vs. input frequency, 1 v p-p input figures 13 and 14 illustrate typical input connections for single- ended inputs. 1 ad872a v ina v inb 2 6 1v figure 13. ad872a single-ended input connection ad872a v ina v inb 6 1v r t 2 1 figure 14. ad872a single-ended input connection using a shielded cable the cable shield is used as a ground connection for the v inb in- put, providing the best possible rejection of the cable noise from the input signal. note also that the high input impedance of the ad872a allows the user to select the termination impedance, be it 50 ohms, or some other value. furthermore, unlike many flash converters, most ad872a applications will not require an external buffer amplifier. if such an amplifier is required, we suggest either the ad811 or ad9617. figure 15 illustrates how external amplifiers may be used to convert a single-ended input into a differential signal. the resis- tor values of 536 w and 562 w were selected to provide opti- mum phase matching between u1 and u2. v in ( 6 0.5v) u2 ad872a 562 v 562 v 536 v 536 v v ina v inb u1 figure 15. single-ended to differential connections; u1, u2 = ad811 or ad9617 the use of the differential input signal can help to minimize even-order distortion from the input tha where performance beyond C70 db is desired. figure 16 shows the ad872a large signal (C0.5 db) and small signal (C20 db) frequency response. input frequency ?hz 10 0 ?0 ?0 ?0 ?0 ?0 fund amp db 10 4 10 5 10 6 10 7 10 8 figure 16. full power (C0.5 db) and small signal response (C20 db) vs. input frequency the ad872as wide input bandwidth facilitates rapid acquisi- tion of transient input signals: the input tha can typically settle to 12-bit accuracy from a full-scale input step in less than 40 ns. figure 17 illustrates the typical acquisition of a full-scale input step. 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 nsec code out figure 17. typical ad872a settling time
rev. a C11C ad872a the wide input bandwidth and superior dynamic performance of the input tha make the ad872a suitable for undersam- pling applications where the input frequency exceeds half the sample frequency. the input tha is designed to recover rap- idly from input overdrive conditions, returning from a 50% overdrive in less than 40 ns. because of the thas exceptionally wide input bandwidth, some users may find the ad872a is sensitive to noise at fre- quencies from 10 mhz to 50 mhz that other converters are inca pable of responding to. this sensitivity can be mitigated by careful use of the differential inputs (see previous paragraphs). additionally, figure 18 shows how a small capacitor (10 pf- 20 pf for 50 w terminated inputs) may be placed between v ina and v inb to help reduce high frequency noise in applications where limiting the input bandwidth is acceptable. 1 2 v ina v inb ad872a 6 1v 10 or 20pf figure 18. optional high frequency noise reduction the ad872a will contribute its own wideband thermal noise. as a result of the integrated wideband noise (0.26 lsb rms, referred-to-input), applying a dc analog input may produce more than one code at the output. a histogram of the adc output codes, for a dc input voltage, will be between one and three codes wide, depending on how well the input is centered on a given code and how many samples are taken. figure 8 shows a typical ad872a code histogram, and figure 9 illus- trates the ad872as transition noise. reference input the nominal reference input should be 2.5 v, taken with re- spect to reference ground (ref gnd). figure 19 il- lustrates the equivalent model for the reference input: there is no clock or signal-dependent activity associated with the refer- ence input circuitry, therefore, no kickback into the reference. 1 2 ref in ref gnd ad872a 5k v ( 6 20%) av ss figure 19. equivalent reference input circuit however, in order to realize the lowest noise performance of the ad872a, care should be taken to minimize noise at the refer- ence input. the ad872as reference input impedance is equal to 5 k w ( 20%), and its effective noise bandwidth is 10 mhz, with a referred-to-input noise gain of 0.8. for example, the internal reference, with an rms noise of 28 m v (using an external 1 m f capacitor), contributes 24 m v (0.05 lsb) of noise to the transfer function of the ad872a. the full-scale peak-to-peak input voltage is a function of the reference voltage, according to the equation: ( v ina = v inb ) full scale = 0. 8 ( v ref ref gnd ) note that the ad872as performance was optimized for a 2.5 v reference input: performance may degrade somewhat for other reference voltages. figure 20 illustrates the s/(n+d) perfor- mance vs. reference voltage for a 1 mhz, C0.5 db input signal. note also that if the reference is changed during a conversion, all three conversions in the pipeline will be invalidated. 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 reference input voltage ?v 75 70 65 60 55 50 s/(n+d) db figure 20. s/(n+d) vs. reference input voltage, f in = 1 mhz, fs = 10 mhz table ii summarizes various 2.5 v references suitable for use with the ad872a, including the onboard bandgap reference (see reference output section). table ii. suitable 2.5 v references drift (ppm/ 8 c) initial accuracy % ref43b 6 (max) 0.2 ad680jn 10 (max) 0.4 internal 30 (typ) 0.4 if an external reference is connected to ref in, ref out must be connected to +5 v. this should lower the current in ref gnd to less than 350 m a and eliminate the need for a 1 m f capacitor, although decoupling the reference for noise reduction purposes is recommended. alternatively, figure 21 shows how the ad872a may be driven from other references by use of an external resistor. the exter- nal resistor forms a resistor divider with the on-chip 5 k w resis- tor to realize 2.5 v at the reference input pin (ref in). a trim potentiometer is needed to accommodate the tolerance of the ad872as 5 k w resistor.
rev. a C12C ad872a ref in ref gnd ad872a +5v ref 2k v 3.9k v r r t 2.5v 5k v figure 21. optional +5 v reference input circuit reference ground the ref gnd pin provides the reference point for both the reference input, and the reference output. when the internal reference is operating, it will draw approximately 500 m a of cur- rent through the reference ground, so a low impedance path to the external common is desirable. the ad872a can tolerate a fairly large difference between ref gnd and agnd, up to +1 v, without any performance degradation. reference output the ad872a features an onboard, curvature compensated bandgap reference that has been laser trimmed for both absolute value and temperature drift. the output stage of the reference was designed to allow the use of an external capacitor to limit the wideband noise. as figure 22 illustrates, a 1 m f capacitor on the reference output is required for stability of the reference output buffer. note: if used, an external reference may become unstable with this capacitor in place. ref in ref gnd ad872a 0.1 m f ref out + 1.0 m f figure 22. typical reference decoupling connection with this capacitor in place, the noise on the reference output is approximately 28 m v rms at room temperature. figure 23 shows the typical temperature drift performance of the reference, while figure 24 illustrates the variation in reference voltage with load currents. the output stage is designed to provide at least 2 ma of out- put current, allowing a single reference to drive up to four ad872as, or other external loads. the power supply rejection of the reference is better than C54 db at dc. 2.55 2.45 125 2.48 2.46 C35 2.47 C55 2.51 2.49 2.50 2.52 2.53 2.54 105 85 65 45 25 5 C15 temperature C 8 c reference voltage C volts figure 23. reference output voltage vs. temperature 2.50 2.40 1m 2.46 2.42 10k 2.44 1k 2.48 100k reference output load C v reference voltage C v figure 24. reference output voltage vs. output load digital outputs in 28-lead packages, the ad872a output data is presented in twos complement format. table iii indicates offset binary and twos complement output for various analog inputs. table iii. output data format analog input digital output v ina Cv inb offset binary twos complement otr 3 0.999756 v 1111 1111 1111 0111 1111 1111 1 0.999268 v 1111 1111 1111 0111 1111 1111 0 0 v 1000 0000 0000 0000 0000 0000 0 C1 v 0000 0000 0000 1000 0000 0000 0 C1.000244 v 0000 0000 0000 1000 0000 0000 1 users requiring offset binary encoding may simply invert the msb pin. in the 44-terminal surface mount packages, both msb and msb bits are provided. the ad872a features a digital out-of-range (otr) bit that goes high when the input exceeds positive full scale or falls below negative full scale. as table iii indicates, the output bits will be set appropriately according to whether it is an out-of-range high
rev. a C13C ad872a condition or an out-of-range low condition. note that if the in- put is driven beyond +1.5 v, the digital outputs may not stay at +fs, but may actually fold back to midscale. the ad872as cmos digital output drivers are sized to pro- vide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the supplies and may affect s/(n+d) performance. applications requiring the ad872a to drive large capacitive loads or large fanout may require additional decoupling capacitors on drv dd and dv dd . in extreme cases, external buffers or latches could be used. three-state outputs the 44-terminal surface mount ad872a offers three-state out- puts. the digital outputs can be placed into a three-state mode by pulling the output enable (oen) pin low. note that this function is not intended to be used to pull the ad872a on and off a bus at 10 mhz. rather, it is intended to allow the adc to be pulled off the bus for evaluation or test modes. also, to avoid corruption of the sampled analog signal during conversion (3 clock cycles), it is highly recommended that the ad872a be placed on the bus prior to the first sampling. data output active three-state oen t dd t hl figure 25. three-state output timing diagram for timing budgetary purposes, the typical access and float de- lay times for the ad872a are 50 ns. clock input the ad872a internal timing control uses the two edges of the clock input to generate a variety of internal timing signals. the optimal clock input should have a 50% duty cycle; however, sensitivity to duty cycle is significantly reduced for clock rates of less than 10 megasamples per second. 20mhz 74xx74 s r q clk +5v +5v q d figure 26. divide-by-two clock circuit due to the nature of on-chip compensation circuitry, the duty cycle should be maintained between 40% and 60% even for clock rates less than 10 msps. one way to realize a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in figure 26. in this case, a 20 mhz clock is divided by 2 to produce the 10 mhz clock input for the ad872a. in this configuration, the duty cycle of the 20 mhz clock is irrelevant. the input circuitry for the clkin pin is designed to accom- modate both ttl and cmos inputs. the quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance for the part: the faster the rising edge, the better the jitter performance. as a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. jitter-induced errors become more pro- nounced at higher frequency, large amplitude inputs, where the input slew rate is greatest. the ad872a is designed to support a sampling rate of 10 msps; running at slightly faster clock rates may be possible, although at reduced performance levels. conversely, some slight performance improvements might be realized by clocking the ad872a at slower clock rates. figure 27 presents the s/(n+d) vs. clock frequency for a 1 mhz analog input. 0 2 4 6 8 10 12 14 16 18 20 s/(n+d) db frequency ?mhz 75 70 65 60 55 50 figure 27. typical s/(n+d) vs. clock frequency, f in = 1 mhz, full-scale input the power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at re- duced clock rates provides a slight reduction in power consump- tion. figure 28 illustrates this tradeoff. 0 2 4 6 8 10 12 14 16 18 20 frequency ?mhz 1.09 1.08 1.07 1.06 1.05 1.04 power ?w figure 28. typical power dissipation vs. clock frequency
rev. a C14C ad872a analog supplies and grounds the ad872a features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. in general, av ss and av dd , the analog supplies, should be decoupled to agnd, the analog common, as close to the chip as physically possible. care has been taken to minimize the signal dependence of the power supply currents; however, the analog supply currents will be proportional to the reference input. with refin at 2.5 v, the typical current into av dd is 85 ma, while the typical current out of av ss is 115 ma. typi- cally, 30 ma will flow into the agnd pin. careful design and the use of differential circuitry provide the ad872a with excellent rejection of power supply noise over a wide range of frequencies, as illustrated in figure 29. frequency ?hz supply rejection ?db ?5 ?0 ?5 ?0 ?5 ?00 av ss av dd dv dd 10 4 10 5 10 6 10 7 figure 29. power supply rejection vs. frequency, 100 mv p-p signal on power supplies figure 30 shows the degradation in snr resulting from 100 mv of power supply ripple at various frequencies. as figure 30 shows, careful decoupling is required to realize the specified dy- namic performance. figure 34 demonstrates the recommended decoupling strategy for the supply pins. note that in extremely noisy environments, a more elaborate supply filtering scheme may be necessary. frequency ?hz snr ?db 70 65 60 55 50 av dd av ss dv dd 10 4 10 5 10 6 10 7 figure 30. snr vs. supply noise frequency (f in = 1 mhz) digital supplies and grounds the digital activity on the ad872a chip falls into two general categories: cmos correction logic, and cmos output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions; in the 44-terminal package, these currents flow through pins dgnd and dv dd . the output drivers draw large current impulses while the output bits are changing. the size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. in the 44-terminal package, the output drivers are supplied through dedicated pins drgnd and drv dd . pin count constraints in the 28-lead packages require that the digital and driver supplies share package pins (although they have sepa- rate bond wires and on-chip routing). the decoupling shown in figure 34 is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pf on each pin). applications involving greater digital loads should consider increasing the digital decoupling proportionately, and/or using external buffers/ latches. applications optional zero and gain trim the ad872a is factory trimmed to minimize zero error, gain error and linearity errors. in some applications the zero and gain errors of the ad872a need to be externally adjusted to zero. if required, both zero error and gain error can be trimmed with ex- ternal potentiometers as shown in figure 31. note that gain er- ror adjustments must be made with an external reference. zero trim should be adjusted first. connect v ina to ground and adjust the 10 k w potentiometer such that a nominal digital out- put code of 0000 0000 0000 (twos complement output) exists. note that the zero trim should be decoupled and that the accu- racy of the 2.5 v reference signals will directly affect the offset. gain error may then be calibrated by adjusting the ref in voltage. the ref in voltage should be adjusted such that a +1 v input on v ina results in the digital output code 01111 1111 1111 (twos complement output). +2.5v C2.5v v inb ad872a 0.1 m f 10 m f 10k v (a) zero trim ref in ad872a trim v out ref43 (b) gain trim 100k v figure 31. zero and gain error trims digital offset correction the ad872a provides differential inputs that may be used to correct any offset voltages on the analog input. for applications where the input signal contains a dc offset, it may be advanta- geous to apply a nulling voltage to the v inb input. applying a voltage equal to the dc offset will maximize the full-scale input range and therefore the dynamic range. offsets ranging from C0.7 v to +0.5 v can be corrected.
rev. a C15C ad872a figure 32 shows how a dc offset can be applied using the ad568 12-bit, high speed digital-to-analog converter (dac). this circuit can be used for applications requiring offset adjust- ments on every clock cycle. the ad568 connection scheme is used to provide a C0.512 v to +0.512 v output range. the off- set voltage must be stable on the rising edge of the ad872a clock input. 1 2 v ina v inb ad872a ibpo iout rl acom lcom ref com ad568 74 hc 574 74 hc 574 8 8 4 4 digital offset word v in figure 32. offset correction using the ad568 undersampling using the ad872a and ad9100 the ad872as on-chip tha optimizes transient response while maintaining low noise performance. for super-nyquist (under- sampling) applications it may be necessary to use an external tha with fast track-mode slew rate and hold mode settling time. an excellent choice for this application is the ad9100, an ultrahigh speed track-and-hold amplifier. in order to maximize the spurious free dynamic range of the circuit in figure 33 it is advantageous to present a small signal to the input of the ad9100 and then amplify the output to the ad872as full-scale input range. this can be accomplished with a low distortion, wide bandwidth amplifier such as the ad9617. the circuit uses a gain of 3.5 to optimize s/(n+d). for small scale input signals (C20 db, C40 db), the ad872a performs better without the track-and-hold because slew- limiting effects are no longer dominant. to gain the advantages of the added track-and-hold, it is important to give the ad872a a full-scale input. an alternative to the configuration presented above is to use the ad9101 track-and-hold amplifier. the ad9101 provides a built-in post amplifier with a gain of 4, providing excellent ac characteristics in conjunction with a high level of integration. as illustrated in figure 33, it is necessary to skew the ad872a sample clock and the ad9100 sample/hold control. clock skew (t s ) is defined as the time starting at the ad9100s transition into hold mode and ending at the moment the ad872a samples. the ad872a samples on the rising edge of the sample clock, and the ad9100 samples on the falling edge of the sample/hold control. the choice of t s is primarily determined by the settling time of the ad9100. the droop rate of the ad9100 must also be taken into consideration. using these values, the ideal t s is 17 ns. when choosing clock sources, it is extremely important that the front end track-and-hold sample/hold control is given a very low jitter clock source. this is not as crucial for the ad872a sample clock, because it is sampling a dc signal. figure 33. undersampling using the ad872a and ad9100 ad9100 2 3 8 10 17 13 12 11 6 15 1 5 7 14 16 20 4 19 18 ad872a eb clock 1 +v s Cv s 1 5 7q 9 10 4 8 q r t 510 510 Cv s Cv s r t +v s 10 m f 10 m f Cv s 127 7 2 3 4 5* 6 8* 0.1 m f 3.3 m f C5v 442 0.1 m f 0.1 m f 0.1 m f 3.3 m f +5v clock 2 * optional, see ad9617 datasheet +v s = 5.0v Cv s = C5.2v all capacitors are 0.01 m f (low inductance - decoupling) unless otherwise noted. t = 200ns clock 2 clock 1 t s = 17ns t s t = 200ns +5v 0v +1v C1v ad 96685 ad 9617 v in a in in in
rev. a C16C ad872a figure 34. ad872a/ad871 evaluation board schematic C5a +5va agnd C5va +5vd dgnd c3 0.01 c10 0.1 c6 fb1 fb2 fb3 c2 0.01 c1 0.01 tp5 tp4 tp7 +5a c9 0.1 c5 22 m f c8 0.1 c4 C5a +5d tp6 tp3 r5 20 clk otr msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 agnd c13 0.1 c15 0.1 v ina v inb ref gnd ref in ref out tp1 j1 analog in r1 49.9 c20 10pf 1 2 27 28 26 c21 1 m f jp2 jp1 c7 10 m f +5a c22 0.1 c18 0.1 av ss av ss 1 2 3 4 8 7 6 5 c12 0.1 +5a 4 5 7 6 22 23 agnd av dd dgnd dgnd drv dd dv dd c14 0.1 c16 0.1 21 20 19 18 17 16 15 14 13 12 11 10 9 8 24 25 3 c11 0.1 c17 0.1 clock input j2 tp2 r2 49.9 +5d r3 10 jp8 jp7 3 4 5 6 jp9 jp10 1 2 jp6 jp5 +5d u3 74hc04 jp3 jp4 p1 40-pin idc conn. r4 r6 20 r7 20 r8 20 r9 20 r10 20 r11 20 r12 20 r13 20 r14 20 r15 20 r16 20 r17 20 40 1 v in gnd v out u2 ref43 jp 11 * * note: jp11 should be open ad872a 22 m f 22 m f
rev. a C17C ad872a figure 35. silkscreen layer pcb layout (not shown to scale) table iv. components list reference designator description quantity r1, r2 resistor, 1%, metal film, 49.9 w 2 r3 resistor, 1%, metal film, 10 1 r4Cr17 resistor, 1%, metal film, 20 14 c1Cc3 smd chip capacitor, 0.01 m f3 c4Cc6 capacitor, tantalum, 22 m f3 c7 capacitor, tantalum, 10 m f1 c8Cc19, c22 smd chip capacitor, 0.1 m f13 c20 capacitor, mica, 10 pf 1 c21 capacitor, ceramic, 1 m f1 u1 ad872a 1 u2 ref43b 1 u3 74hc04n 1 fb1Cfb3 ferrite bead 3 j1, j2 bnc jack 2 jp2, 3, 5, 7, 10 jumpers 5 jp1Cjp11 headers 11 p1 40-pin idc connector 1
rev. a C18C ad872a figure 37. solder side pcb layout (not shown to scale) figure 36. component side pcb layout (not shown to scale)
rev. a C19C ad872a figure 38. ground layer pcb layout (not shown to scale) figure 39. power layer pcb layout (not shown to scale)
rev. a C20C ad872a outline dimensions dimensions shown in inches and (mm). 28-lead side brazed dip (d-28) 0.610 (15.49) 0.500 (12.70) 14 0.100 (2.54) max 15 pin 1 1 0.005 (0.13) min 28 0.225 (5.72) max 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 1.490 (37.85) max 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) 44-terminal lcc (e-44a) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) ref 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc bottom view 1 28 18 0.040 (1.02) ref x 45 3 places 0.028 (0.71) 0.022 (0.56) 0.020 (0.51) ref x 45 640 0.662 (16.82) 0.640 (16.27) sq c2001aC0C11/97 printed in u.s.a.

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